There is a trend in hand-held devices for mobile communications towards Systems on Chip (SoCs), meaning that the digital baseband (BB) sub system and the RF sub system are integrated on a single chip in CMOS technology. Traditionally, these two subsystems were implemented on dedicated chips in CMOS and BiCMOS technology, respectively. SoCs promise cost reduction, provided the high yield known from purely digital chips is reached:
The RF subsystem is characterized by several figures of merit, such as image rejection or noise figure. If one of the figures of merits of a given chip is outside the specified range, then this chip is bad and reduces the yield. Since the yield in analogue chips is usually lower than in digital chips, measures for yield improvement are required. This leads to heavy use of calibration techniques and digital signal processing.
Receivers in today's cellular phones employ a single analogue conversion stage from RF to baseband. The receivers distinguish in the choice of the Intermediate Frequency (IF) of the analogue baseband signal before digitization. For example, Low IF in 2G and 2.5G cellular applications may be used. However, after RF BiCMOS technology progressed and certain problems disappeared that Low IF avoided, Zero IF is an option as well. With the switch to CMOS technology, these problems recurred and/or new problems came up, with the consequence that some manufacturers have changed from Zero IF to Low IF in their 2.5G cellular products.
However, there may be a need to provide a data signal processing device and method that can improve raw image rejection in a Low IF receiver, in particular by using digital processing.